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| ? 2008 microchip technology inc. preliminary ds22077b-page 1 24AA014H/24lc014h device selection table features: single-supply with operation down to 1.7v low-power cmos technology: - 400 a active current, maximum -1 a standby current, maximum (i-temp) organized as a single block of 128 bytes (128 x 8) 2-wire serial interface bus, i 2 c? compatible schmitt trigger inputs for noise suppression output slope control to eliminate ground bounce 100 khz and 400 khz compatibility 1 mhz compatibility (lc) page write buffer for up to 16 bytes self-timed write cycle (including auto-erase) hardware write protection for half array (40h-7fh) address lines allow up to eight devices on bus 1 million erase/write cycles esd protection > 4,000v data retention > 200 years factory programming (qtp) available pb-free and rohs compliant 8-pin pdip, soic, tssop, tdfn and msop packages available for extended temperature ranges: description: the microchip technology inc. 24AA014H/24lc014h is a 1 kbit serial electrically erasable prom with operation down to 1.7v. the device is organized as a single block of 128 x 8-bit memory with a 2-wire serial interface. low-current design permits operation with maximum standby and active currents of only 1 a and 400 a, respectively. the device has a page write capability for up to 16 bytes of data. functional address lines allow the connection of up to eight 24AA014H/ 24lc014h devices on the same bus for up to 8 kbits of contiguous eeprom memory. the device is available in the standard 8-pin pdip, 8-pin soic (150 mil), tssop, 2x3 tdfn and msop packages. package types block diagram part number v cc range max. clock temp. range 24AA014H 1.7v-5.5v 400 khz (1) i 24lc014h 2.5v-5.5v 1 mhz i, e note 1: 100 khz for v cc < 1.8v - industrial (i): -40c to +85c - automotive (e): -40c to +125c a0a1 a2 v ss v cc wpscl sda 12 3 4 87 6 5 pdip, msop soic, tssop a0a1 a2 v ss 12 3 4 87 6 5 v cc wpscl sda tdfn a0 a1 a2 v ss wp sclsda v cc 87 6 5 1 2 3 4 i/o control logic memory control logic xdec hv generator eeprom array write-protect circuitry ydec v cc v ss sense amp. r/w control sda scl a0 a1 a2 wp 1k i 2 c ? serial eeprom with half-array write-protect downloaded from: http:///
24AA014H/24lc014h ds22077b-page 2 preliminary ? 2008 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-40c to +125c esd protection on all pins .................................................................................................... .................................................. 4 kv ? notice : stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions abo ve those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: dc characteristics all parameters apply across the specified operating ranges unless otherwise noted. electrical characteristics: industrial (i): v cc = +1.7v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to +125c parameter symbol min. max. units conditions scl and sda pins: high-level input voltage v ih 0.7 v cc v low-level input voltage v il 0.3 v cc v hysteresis of schmitt trigger inputs v hys 0.05 v cc v (note 1) low-level output voltage v ol 0 . 4 0vi ol = 3.0 ma, v cc = 4.5v i ol = 2.1 ma, v cc = 2.5v input leakage current i li 1 ? v in = v ss or v cc , wp = vss output leakage current i lo 1 av out = v ss or v cc pin capacitance (all inputs/outputs) c in , c out 1 0p f v cc = 5.0v (note 1) t a = 25c, f = 1 mhz operating current i cc read 400 av cc = 5.5v, scl = 400 khz i cc write 3 ma v cc = 5.5v standby current i ccs 1 av cc = 5.5v, sda = scl = v cc wp = v ss , a0, a1, a2 = v ss note 1: this parameter is periodically sampled and not 100% tested. downloaded from: http:/// ? 2008 microchip technology inc. preliminary ds22077b-page 3 24AA014H/24lc014h table 1-2: ac characteristics ac characteristics electrical characteristics: industrial (i): v cc = +1.7v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to +125c param. no. symbol characteristic min. max. units conditions 1f clk clock frequency 100400 1000 khz 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 2t high clock high time 4000 600500 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 3t low clock low time 4700 1300 500 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 4t r sda and scl rise time (note 1) 1000 300300 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 5t f sda and scl fall time (note 1) 1000 300300 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 6t hd : sta start condition hold time 4000 600250 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 7t su : sta start condition setup time 4700 600250 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 8t hd : dat data input hold time 0 ns (note 2) 9t su : dat data input setup time 250 100100 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 10 t su : sto stop condition setup time 4000 600250 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 11 t su : wp wp setup time 4000 600600 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 12 t hd : wp wp hold time 4700 600600 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 13 t aa output valid from clock (note 2) 3500 900400 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 14 t buf bus free time: time the bus must be free before a new transmission can start 13004700 4700 ns 1.7v v cc < 1.8v 1.8v v cc 5.5v 2.5v v cc 5.5v (24lc014h) 16 t sp input filter spike suppression (sda and scl pins) 50 ns 24AA014H (note 1 and note 3) 17 t wc write cycle time (byte or page) 5 ms 18 endurance 1m cycles 25c, v cc = 5.5v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal mi nimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs, which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained from microchips web site at www.microchip.com. downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 4 preliminary ? 2008 microchip technology inc. figure 1-1: bus timing data (unprotected) (protected) scl sda in sda out wp 5 7 6 16 3 2 89 13 d4 4 10 11 12 14 downloaded from: http:/// ? 2008 microchip technology inc. preliminary ds22077b-page 5 24AA014H/24lc014h 2.0 pin descriptions the descriptions of the pins are listed in table 2-1. table 2-1: pin function table 2.1 sda serial data this is a bidirectional pin used to transfer addresses and data into and out of the device. it is an open drain terminal. therefore, the sda bus requires a pull-up resistor to v cc (typical 10 k for 100 khz, 2 k for 400 khz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 2.2 scl serial clock the scl input is used to synchronize the data transfer to and from the device. 2.3 a0, a1, a2 the a0, a1 and a2 inputs are used by the 24AA014H/ 24lc014h for multiple device operations. the levels on these inputs are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. up to eight 24AA014H/24lc014h devices may be connected to the same bus by using different chip select bit combinations. these inputs must be connected to either v cc or v ss . in most applications, the chip address inputs a0, a1 and a2 are hard-wired to logic 0 or logic 1 . for applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic 0 or logic 1 before normal device operation can proceed. 2.4 wp wp is the hardware write-protect pin. it must be tied to v cc or v ss . if tied to v cc , the hardware write protection is enabled and will protect half of the array (40h-7fh). if the wp pin is tied to v ss the hardware write protection is disabled. 2.5 noise protection the 24AA014H/24lc014h employs a v cc threshold detector circuit that disables the internal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits that suppress noise spikes to assure proper device operation even on a noisy bus. name 8-pin pdip 8-pin soic 8-pin tssop 8-pin msop 8-pin tdfn function a0 1 1 1 1 1 user configurable chip select a1 2 2 2 2 2 user configurable chip select a2 3 3 3 3 3 user configurable chip select v ss 4444 4 g r o u n d sda 5 5 5 5 5 serial data scl 6 6 6 6 6 serial clock wp 7 7 7 7 7 write-protect input v cc 8 8 8 8 8 +1.7v to 5.5v (24AA014H) +2.5v to 5.5v (24lc014h) downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 6 preliminary ? 2008 microchip technology inc. 3.0 functional description the 24AA014H/24lc014h supports a bidirectional, 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device that generates the serial clock (scl), controls the bus access and gen- erates the start and stop conditions while the 24AA014H/24lc014h works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 4.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 4-1). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is, theoretically, unlimited, though only the last sixteen will be stored when doing a write operation. when an overwrite does occur, it will replace data in a first-in first-out fashion. 4.5 acknowledge each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition (figure 4-2). figure 4-1: data transfer sequence on the serial bus characteristics note: the 24AA014H/24lc014h does not gen- erate any acknowledge bits if an internal programming cycle is in progress. (a) (b) (c) (d) (a) (c) scl sda start condition address or acknowledge valid data allowed to change stop condition downloaded from: http:/// ? 2008 microchip technology inc. preliminary ds22077b-page 7 24AA014H/24lc014h figure 4-2: acknowledge timing scl 9 8 7 6 5 4 3 2 1 123 transmitter must release the sda line at this point allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. sda acknowledge bit data from transmitter data from transmitter downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 8 preliminary ? 2008 microchip technology inc. 5.0 device addressing a control byte is the first byte received following the start condition from the master device (figure 5-1). the control byte consists of a four-bit control code; for the 24AA014H/24lc014h this is set as 1010 binary for read and write operations. the next three bits of the control byte are the chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 24AA014H/ 24lc014h devices on the same bus and are used to select which device is accessed. the chip select bits in the control byte must correspond to the logic levels on the corresponding a2, a1 and a0 pins for the device to respond. these bits are in effect the three most significant bits of the word address. the last bit of the control byte defines the operation to be performed. when set to a 1 , a read operation is selected. when set to a 0 , a write operation is selected. following the start condition, the 24AA014H/ 24lc014h monitors the sda bus, checking the control byte being transmitted. upon receiving a 1010 code and appropriate chip select bits, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24AA014H/ 24lc014h will select a read or write operation. figure 5-1: control byte format 5.1 contiguous addressing across multiple devices the chip select bits a2, a1 and a0 can be used to expand the contiguous address space for up to 8k bits by adding up to eight 24AA014H/24lc014h devices on the same bus. in this case, software can use a0 of the control byte as address bit a8, a1 as address bit a9, and a2 as address bit a10. it is not possible to sequentially read across device boundaries. 1010 a2 a1 a0 sa c k r/w control code chip select bits slave address acknowledge bit start bit read/write bit downloaded from: http:/// ? 2008 microchip technology inc. preliminary ds22077b-page 9 24AA014H/24lc014h 6.0 write operations 6.1 byte write following the start signal from the master, the device code(4 bits), the chip select bits (3 bits) and the r/w bit (which is a logic low) are placed onto the bus by the master transmitter. the device will acknowledge this control byte during the ninth clock pulse. the next byte transmitted by the master is the word address and will be written into the address pointer of the 24AA014H/ 24lc014h. after receiving another acknowledge signal from the 24AA014H/24lc014h, the master device will transmit the data word to be written into the addressed memory location. the 24AA014H/ 24lc014h acknowledges again and the master generates a stop condition. this initiates the internal write cycle and the 24AA014H/24lc014h will not generate acknowledge signals during this time (figure 6-1). if an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. the write cycle time must be observed even if write protection is enabled. 6.2 page write the write-control byte, word address and the first data byte are transmitted to the 24AA014H/24lc014h in the same way as in a byte write. but instead of generating a stop condition, the master transmits up to 15 additional data bytes to the 24AA014H/24lc014h that are temporarily stored in the on-chip page buffer and will be written into the memory once the master has transmitted a stop condition. upon receipt of each word, the four lower order address pointer bits are internally incremented by one. the higher order four bits of the word address remain constant. if the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received, an internal write cycle will begin (figure 6-2). if an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. the write cycle time must be observed even if write protection is enabled. 6.3 write protection the wp pin must be tied to v cc or v ss . if tied to v cc , half of the array will be write-protected (40h-7fh). if the wp pin is tied to v ss , write operations to all address locations are allowed. figure 6-1: byte write figure 6-2: page write note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page size) and end at addresses that are integer multiples of [page size C 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. it is therefore necessary that the application software prevent page write operations that would attempt to cross a page boundary. s p bus activity master sda line bus activity st a r t st o p control byte word address data ac k ac k ac k s p bus activity master sda line bus activity st a r t control byte word address (n) data (n) data (n + 15) st o p ac k ac k ac k ac k ac k data (n +1) downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 10 preliminary ? 2008 microchip technology inc. 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally-timed write cycle and ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, no ack will be returned. if no ack is returned, the start bit and control byte must be re-sent. if the cycle is complete, the device will return the ack and the master can then proceed with the next read or write command. see figure 7-1 for a flow diagram of this operation. figure 7-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes downloaded from: http:/// ? 2008 microchip technology inc. preliminary ds22077b-page 11 24AA014H/24lc014h 8.0 read operations read operations are initiated in the same way as write operations, with the exception that the r/w bit of the slave address is set to 1 . there are three basic types of read operations: current address read, random read and sequential read. 8.1 current address read the 24AA014H/24lc014h contains an address coun- ter that maintains the address of the last word accessed, internally incremented by one. therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with the r/w bit set to 1 , the 24AA014H/24lc014h issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24AA014H/ 24lc014h discontinues transmission (figure 8-1). 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the word address must first be set. this is done by sending the word address to the 24AA014H/24lc014h as part of a write operation. once the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. the master then issues the control byte again but with the r/w bit set to a 1 . the 24AA014H/24lc014h will then issue an acknowledge and transmits the eight-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24AA014H/ 24lc014h discontinues transmission (figure 8-2). after this command, the internal address counter will point to the address location following the one that was just read. 8.3 sequential read sequential reads are initiated in the same way as a random read except that after the 24AA014H/ 24lc014h transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24AA014H/ 24lc014h to transmit the next sequentially addressed 8-bit word (figure 8-3). to provide sequential reads the 24AA014H/24lc014h contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. the internal address pointer will automatically roll over from address 07fh to address 000h. figure 8-1: current address read bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 12 preliminary ? 2008 microchip technology inc. figure 8-2: random read figure 8-3: sequential read s p s bus activity master sda line bus activity st a r t s t o p control byte a c k word address (n) control byte s t a r t data (n) a c k a c k n o a c k bus activity master sda line bus activity control byte data (n) data (n + 1) data (n + 2) data (n + x) no a c k ac k ac k ac k ac k s t o p p downloaded from: http:/// ? 2008 microchip technology inc. preliminary ds22077b-page 13 24AA014H/24lc014h 9.0 packaging information 9.1 package marking information xxxxxxxx t/xxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (3.90 mm) example: xxxxxxxt xxxxyyww nnn 8-lead tssop example: 24lc014h i/p 12f 0821 24l014hi sn 0821 12f 8-lead msop example: xxxx tyww nnn l14h i821 12f 4l14hi 82112f xxxxt ywwnnn 3 e 3 e 8-lead 2x3 tdfn example: ak4821 12 xxx yww nn downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 14 preliminary ? 2008 microchip technology inc. part number 1st line marking codes tssop msop tdfn ie i e ie 24AA014H a14a 4a14hi ak1 24lc014h l14h l14a 4l14hi 4l14he ak4 ak5 note: t = temperature grade (i, e) legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e note: please visit www.microchip.com/pbfree for the latest information on pb-free conversion. * standard otp marking consists of microchip part number, year code, week code, and traceabili ty code. downloaded from: http:/// ? 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'! 9'&! 7 7: ; 7"') % ! 7 < & 1, & & = = ## 4 4!! - 1 !& & = = "# & "# >#& . - - ## 4 >#& . < : 9& -< -? & & 9 - 9 # 4!! < 6 9 #>#& ) ? 9 * 9 #>#& ) < : * + 1 = = - n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c * , <1 downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 16 preliminary ? 2008 microchip technology inc. ! ""#$%& !' !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & 1, : 8 & = = ## 4 4!! = = & # %% + = : >#& . ?1, ## 4 >#& . -1, : 9& 1, , '% @ & a = 3 &9& 9 = 3 & & 9 .3 3 & b = #& ) - = # %& b = b # %&1 && ' b = b d n e e e1 note 1 12 3 b a a1 a2 l l1 c h h * , 1 downloaded from: http:/// ? 2008 microchip technology inc. preliminary ds22077b-page 17 24AA014H/24lc014h ! ""#$%& !' 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 18 preliminary ? 2008 microchip technology inc. () )" * ! (+%+ ( ! !" #$% &" ' ()"&'"!&) &#*& & & # '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# - '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & ? 1, : 8 & = = ## 4 4!! < & # %% = : >#& . ?1, ## 4 >#& . - ## 4 9& - - 3 &9& 9 ? 3 & & 9 .3 3 & b = #& ) = - d n e e1 note 1 12 b e c a a1 a2 l1 l * , ? 2008 microchip technology inc. preliminary ds22077b-page 19 24AA014H/24lc014h , " ! *-, , ! !" #$% &" ' ()"&'"!&) &#*& & & # '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# - '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & ? 1, : 8 & = = ## 4 4!! < & # %% = : >#& . 1, ## 4 >#& . -1, : 9& -1, 3 &9& 9 ? < 3 & & 9 .3 3 & b = #& ) = d n e e1 note 1 1 2 e b a a1 a2 c l1 l * , 1 downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 20 preliminary ? 2008 microchip technology inc. . $ *-, /00%12 (. 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 downloaded from: http:/// ? 2008 microchip technology inc. preliminary ds22077b-page 21 24AA014H/24lc014h . $ *-, /00%12 (. 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 22 preliminary ? 2008 microchip technology inc. revision history revision a (03/2008) original release. revision b (09/2008) added new pin function table; corrections on dc characteristics table; updated section 2.3. downloaded from: http:/// ? 2008 microchip technology inc. preliminary ds22077b-page 23 24AA014H/24lc014h the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 24 preliminary ? 2008 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microc hip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our document ation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this docume nt. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds22077b 24AA014H/24lc014h 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? downloaded from: http:/// ? 2008 microchip technology inc. preliminary ds22077b-page 25 24AA014H/24lc014h product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: 24AA014H: 1.7v, 1 kbit addressable serial eeprom 24AA014Ht: 1.7v, 1 kbit addressable serial eeprom (tape and reel) 24lc014h: 2.5v, 1 kbit addressable serial eeprom 24lc014ht: 2.5v, 1 kbit addressable serial eeprom (tape and reel) temperature range: i = -40c to +85c e = -40c to +125c package: p = plastic dip, (300 mil body), 8-lead sn = plastic soic, (3.90 mm body) st = tssop, (4.4 mm body), 8-lead ms = msop, (plastic micro small outline), 8-lead mny (1) = tdfn, (2x3x0.75 mm body), 8-lead part no. x /xx package temperature range device examples: a) 24AA014H-i/p: industrial temperature, 1.7v, pdip package. b) 24AA014H-i/sn: industrial temperature, 1.7v, soic package. c) 24AA014Ht-i/st: industrial tempera- ture, 1.7v, tssop package, tape and reel a) 24lc014h-i/p: industrial temperature, 2.5v, pdip package. b) 24lc014ht-e/sn: automotive tempera- ture, 2.5v, soic package, tape and reel c) 24lc014ht-i/ms: industrial tempera- ture, 2.5v, msop package, tape and reel. note 1: y indicates a nickel palladium gold (nipdau) finish. downloaded from: http:/// 24AA014H/24lc014h ds22077b-page 26 preliminary ? 2008 microchip technology inc. notes: downloaded from: http:/// ? 2008 microchip technology inc. preliminary ds22077b-page 27 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic, smartshunt and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:/// ds22077b-page 28 preliminary ? 2008 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 01/02/08 downloaded from: http:/// |
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